What are the key updates in the AI chipmaking market, including TSMC's interposer deal, High-NA production, and lead times?
The Month in Numbers
TSMC posted record September revenue, up 54.6% year over year, and a record third quarter of NT$1.49 trillion, roughly $46.7 billion, with full results due October 15. Data center capex rose 92% year over year in the second quarter against roughly $720 billion of committed 2026 spending across Amazon, Alphabet, Microsoft and Meta. SEMI forecasts global equipment sales of $165.9 billion in 2026, $201.2 billion in 2027 and $229.5 billion in 2028, versus $135.1 billion of actual billings in 2025. Inputs are tightening: substrates up 20%, copper-clad laminates up 30%, UBS warning silicon wafer prices rise 40% by 2027, Samsung HBM4 pricing reported starting near $4.50 per gigabit, and memory executives expecting shortage through 2028.
TSMC Pays GlobalFoundries About $2 Billion for Interposers
TSMC and GlobalFoundries announced an agreement on October 8 for GlobalFoundries to supply silicon interposers into TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) ecosystem, reported at roughly $2 billion, with production in New York. It is the first U.S.-based source for the component. TSMC’s own CoWoS capacity is tracking to roughly double to 260,000 wafers by 2028.
An interposer is the silicon bridge carrying the thousands of connections between logic die and memory stacks. Every CoWoS package needs one, and supply has sat inside a handful of Taiwanese facilities. TSMC outsourcing it concedes that packaging cannot scale fast enough in-house. Taiwan broke ground on an advanced packaging park in September and ASE is running a capex plan near $10.5 billion. Packaging is now absorbing capital at a rate once reserved for lithography.
High-NA EUV Stopped Being a Research Program
Intel disclosed it has processed more than one million wafers on High-NA EUV and has the technology in production on its 1.8nm flow. Samsung and SK Hynix are expected in volume by 2028. TSMC is reported to be waiting until roughly 2030.
High-NA machines run near $400 million and have spent three years as the industry’s most expensive open question. A million production wafers answers it for one customer. The staggered adoption curve matters for the model: this is revenue that builds across years rather than arriving as a step function. ASML separately said it sold essentially nothing into Europe in 2026 and asked the EU to help create domestic demand.
What are the upstream constraints impacting semiconductor equipment lead times and supply?
Lead times for some South Korean semiconductor equipment components have stretched to 40 months, with vendors warning the delays threaten fab expansion schedules. Substrate prices rose 20% and laminates 30%, Samsung Electro-Mechanics committed roughly 6.78 trillion won to substrate expansion, and Broadcom and Toppan opened Singapore’s first advanced substrate plant.
A 40-month part lead time means a fab planned today is not equipped until 2030. It also means tool backlogs are more durable than any demand-pacing debate implies, because orders placed under those conditions do not get casually cancelled. The chokepoints have migrated into the unglamorous layers, and that is inflationary for everyone building capacity while favoring suppliers already qualified and shipping.
Test and Measurement Became the Scarcest Layer
DISCO reported July through September shipments up 60% to a record. Advantest extended gains as Micron’s results pulled buying into test, and Korean reporting described surging memory tester demand in the HBM era.
Chip stacking changed the economics of test. An HBM stack has to be verified at the die level before bonding, because one bad die ruins a finished package worth many multiples of its value. More layers means more known-good-die testing, more thinning and dicing, more metrology between steps. Those steps scale with stack height rather than wafer volume, which is why the back end of the chipmaking chain is outrunning the front.
Chipmaking Stocks Making Moves
The month split in two: a sharp September 14 drawdown, with Applied Materials and Lam Research down about 6% and ASML down 5%, then a full recovery on records out of TSMC, Micron and the Japanese tool makers.
- Applied Materials (AMAT) added Intel, Besi, Kioxia and UCLA as partners at its EPIC Center, the Silicon Valley research facility with capital spending scaling toward roughly $5 billion, and hosts an investor breakfast at SEMICON West on October 13.
- Lam Research (LRCX) raised its quarterly dividend 27% to $0.33 per share, payable October 14, which is not what a company does while worried about next year’s wafer fab equipment spending. September quarter results land October 21.
- ASML (ASML) reports October 14 against expectations near 55% sales growth, with the High-NA milestones at Intel strengthening the case and the European demand gap working against it.
- Advantest (6857 JP) and Tokyo Electron (8035 JP) both ran with the test and AI cycle, with Tokyo Electron’s CFO signaling a record year toward one trillion yen in operating profit, a completed five-for-one split, and results due October 30.
What is the bottom line summary of the AI chipmaking market updates?
TSMC paying roughly $2 billion for U.S.-made interposers. Intel past a million High-NA wafers while TSMC waits for 2030. Korean part lead times at 40 months, substrates up 20%, wafers forecast up 40% by 2027. DISCO shipments up 60%. TSMC at a record NT$1.49 trillion quarter. The AI pacing scare lasted three weeks, and what replaced it is a supply chain where the scarcity sits in the steps that happen after the wafer is printed.
